An integrated circuit may contain a palladium layer in the interconnect region, for example as a cap layer of a bond pad at the top surface of the integrated circuit, or as an interconnect element in the interconnect region. The palladium layer may be formed by forming a palladium layer in a recess and on an existing top surface of the integrated circuit, followed by a chemical mechanical polish (CMP) operation to remove unwanted palladium from the top surface, leaving palladium in the recess. Attaining desired removal rates of palladium using a CMP operation may require polish pad pressures and speeds which may undesirably reduce pad life and increase fabrication cost of the integrated circuit.